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74LVQ299
8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
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HIGH SPEED: tPD = 8.3 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 299 IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74LVQ299M T&R 74LVQ299MTR 74LVQ299TTR
DESCRIPTION The 74LVQ299 is a low voltage CMOS 8 BIT PIPO SHIFT REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. PIN CONNECTION AND IEC LOGIC SYMBOLS
These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA). Each mode is chosen by two function select inputs (S0, S1) as shown in the Truth Table. When one or both enable inputs, (G1, G2) are high, the eight input/output terminals are in the high impedance state; however sequential operation or clearing of the register is not affected. Clear function is asynchronous to clock. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
July 2001
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74LVQ299
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 11 12 18 10 20 SYMBOL S0, S1 G1, G2 A/QA to H/QH QA',QH' CLEAR SR CLOCK SL GND VCC NAME AND FUNCTION Mode Select Inputs 3-State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver) Serial Outputs (Standard Output) Asynchronous Master Reset Input (Active LOW) Serial Data Shift Right Input Clock Input (LOW to HIGH, Edge-triggered) Serial Data Shift Left Input Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS MODE CLEAR Z CLEAR HOLD SHIFT RIGHT SHIFT LEFT LOAD L L L H H H H H H FUNCTION SELECTED S1 H L X L L L H H H S0 H X L L H H L L H OUTPUT CONTROL G1* X L L L L L L L X G2* X L L L L L L L X X X X X INPUTS/OUTPUTS SERIAL CLOCK SL X X X X X X H L X SR X X X X H L X X X Z L L QA0 H L QBn QBn a Z L L QH0 QGn QGn H L h L L L QA0 H L QBn QBn a L L L QH0 QGn QGn H L h A/QA H/QH QA' QH' OUTPUTS
* When one or both controls are high, the eight input/output terminals are the high impedance state: however sequential operation or cleaning of the register is not affected. Z : High Impedance Qn0 : The level of An before the indicated steady state input conditions were established. Qnn : The level of Qn before the most recent active transition indicated by OR a, h : The level of the steady state inputs A, H, respectively. X : Don't Care
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74LVQ299
LOGIC DIAGRAM
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74LVQ299
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 50 400 -65 to +150 300 Unit V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.0V (note 2) Parameter Value 2 to 3.6 0 to VCC 0 to VCC -55 to 125 0 to 10 Unit V V V C ns/V
1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V
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74LVQ299
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) TA = 25C Min. 2.0 0.8 IO=-50 A 3.0 IO=-12 mA IO=-24 mA VOL Low Level Output Voltage IO=50 A 3.0 IO=12 mA IO=24 mA II IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) 3.6 3.6 3.6 3.6 VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND VOLD = 0.8 V max VOHD = 2 V min 0.1 0.25 4 36 -25 0.002 0 0.1 0.36 2.9 2.58 2.99 2.9 2.48 2.2 0.1 0.44 0.55 1 2.5 40 25 -25 Typ. Max. Value -40 to 85C Min. 2.0 0.8 2.9 2.48 2.2 0.1 0.44 0.55 1 5.0 40 A A A mA mA V V Max. -55 to 125C Min. 2.0 0.8 Max. V V Unit
VIH VIL VOH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
3.0 to 3.6
ICC IOLD IOHD
1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 3.3 CL = 50 pF 3.3 0.8 V TA = 25C Min. Typ. 0.5 -0.8 2 -0.6 Max. 0.8 V V Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
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74LVQ299
AC ELECTRICAL CHARACTERISTICS(CL = 50 pF, R L = 500 , Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 2.7 3.3
(*)
Value TA = 25C Min. Typ. 9.7 8.2 9.8 8.3 8.4 7.1 8.9 7.4 9.9 8.0 9.8 8.0 5.0 4.0 5.0 4.0 4.0 3.0 1.0 1.0 6.0 5.0 1.0 1.0 4.0 3.0 1.0 1.0 1.0 1.0 100 120 2.1 2.0 2.1 2.0 1.4 1.1 -1.3 -1.0 3.1 2.5 -3.1 -2.6 1.5 1.1 -1.5 -1.1 -0.7 -0.5 150 180 0.5 0.5 1.0 1.0 Max. 15.0 12.0 15.0 12.0 14.0 11.0 15.0 12.0 15.0 12.0 15.0 12.0 5.0 4.0 5.0 4.0 4.0 3.0 1.0 1.0 6.0 5.0 1.0 1.0 4.0 3.0 1.0 1.0 1.0 1.0 80 100 1.0 1.0 -40 to 85C Min. Max. 17.5 14.0 17.5 14.0 16.5 13.0 17.5 14.0 17.5 14.0 17.5 14.0 5.0 4.0 5.0 4.0 4.0 3.0 1.0 1.0 6.0 5.0 1.0 1.0 4.0 3.0 1.0 1.0 1.0 1.0 60 80 1.0 1.0 ns ns ns ns ns ns -55 to 125C Min. Max. 20.0 16.5 20.0 16.5 19.0 15.0 20.0 16.5 20.0 16.5 20.0 16.5 ns ns ns ns ns ns Unit
tPLH tPHL Propagation Delay Time CLOCK to Q'A or Q'H tPLH tPHL Propagation Delay Time CLOCK to A/QA, H/QH tPHL Propagation Delay Time CLEAR to Q'A or Q'H Propagation Delay Time CLEAR to A/QA, H/QH tPZL tPZH Output Enable Time G1 or G2 to A/QA, H/QH tPLZ tPHZ Output Disable Time G1 or G2 to A/QA, H/QH tW CLEAR Pulse Width LOW tW ts CLOCK Pulse Width LOW Setup Time HIGH or LOW (A/QA, H/ QH to CLOCK) Hold Time HIGH or LOW (A/QA, H/QH to CLOCK) Setup Time HIGH or LOW (S0 or S1 to CLOCK) Hold Time HIGH or LOW (S0 or S1 to CLOCK) Setup Time HIGH or LOW (SR or SL to CLOCK) Hold Time HIGH or LOW (SR or SL to CLOCK) Recovery Time CLEAR to CLOCK Maximum Clock Frequency Output To Output Skew Time (note1, 2) tPHL
2.7 3.3(*) 2.7 3.3(*) 2.7 3.3
(*)
2.7 3.3
(*)
2.7 3.3(*) 2.7 3.3 2.7 3.3 2.7 3.3
(*)
ns ns
(*)
(*)
th
2.7 3.3(*) 2.7 3.3
(*)
ts
th
2.7 3.3
(*)
ts
2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3
(*)
th
tREM fMAX tOSLH tOSHL
ns ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, t OSHL = |tPHLm - t PHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V 0.3V
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74LVQ299
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 3.3 TA = 25C Min. Typ. 4 Max. Value -40 to 85C Min. Max. -55 to 125C Min. Max. pF pF 3.3 fIN = 10MHz 10 pF Unit
CIN CI/O CPD
Input Capacitance Bus Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit)
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open 2VCC Open
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74LVQ299
WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 2 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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74LVQ299
WAVEFORM 3 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 4 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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74LVQ299
SO-20 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.020 13.00 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.393 0.050 0.450 0.300 0.050 0.029 0.512 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch
PO13L
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74LVQ299
TSSOP20 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.260 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0087225C
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74LVQ299
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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